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PSD4253G3-90UI 데이터 시트보기 (PDF) - STMicroelectronics

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PSD4253G3-90UI Datasheet PDF : 89 Pages
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PSD4235G2
Table 29. Instructions
Instruction14
FS0-FS7 or
CSBOOT0-
CSBOOT3
Cycle 1
Cycle 2 Cycle 3
Cycle 4
Cycle 5 Cycle 6 Cycle 7
Read5
1
“Read”
RD @ RA
Read Main Flash ID6
1
AAh@
XAAAh
55h@
X554h
90h@ Read ID
XAAAh @ XX02h
Read Sector
Protection6,8,13
1
AAh@
XAAAh
55h@
X554h
90h@
XAAAh
Read 00h
or 01h @
XX04h
Program a Flash
Word13
1
AAh@
XAAAh
55h@
X554h
A0h@
XAAAh
PD@ PA
Flash Sector Erase7,13
1
AAh@
XAAAh
55h@
X554h
80h@ AAh@
XAAAh XAAAh
55h@ 30h@
X554h SA
30h7@
next SA
Flash Bulk Erase13
1
AAh@
XAAAh
55h@
X554h
80h@ AAh@
XAAAh XAAAh
55h@
X554h
10h@
XAAAh
Suspend Sector
Erase11
1
B0h@
XXXXh
Resume Sector
Erase12
1
30h@
XXXXh
Reset6
1
F0h@
XXXXh
Unlock Bypass
Unlock Bypass
Program9
1
AAh@
XAAAh
55h@
X554h
20h@
XAAAh
1
A0h@
XXXXh
PD@ PA
Unlock Bypass
Reset10
1
90h@
XXXXh
00h@
XXXXh
Note: 1. All bus cycles are write bus cycles, except the ones with the “Read” label
2. All values are in hexadecimal:
X = Don’t Care. Addresses of the form XXXXh, in this table, must be even addresses
RA = Address of the memory location to be read
RD = Data read from location RA during the Read cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of Write Strobe (WR, CNTL0).
PA is an even address for PSD in word programming mode.
PD = Data word to be programmed at location PA. Data is latched on the rising edge of Write Strobe (WR , CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be
erased, or verified, must be Active (High).
3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft Express.
4. Only address bits A11-A0 are used in instruction decoding.
5. No Unlock or instruction cycles are required when the device is in the Read mode
6. The Reset instruction is required to return to the Read mode after reading the Flash ID, or after reading the Sector Protection Status,
or if the Error Flag (DQ5/DQ13) bit goes High.
7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80 µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1,A0)=(1,0)
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass
mode.
11. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is
intended. The MCU must fetch, for example, the code from the secondary Flash memory when reading the Sector Protection Status
of the primary Flash memory.
14. All write bus cycles in an instruction are byte write to an even address (XA4Ah or X554h). A Flash memory Program bus cycle writes
a word to an even address.
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