ST72E632K2B0 데이터 시트보기 (PDF) - STMicroelectronics

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ST72E632K2B0

LOW SPEED USB 8-BIT MCU FAMILY with up to 16K MEMORY, up to 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI & I2C

STMicroelectronics 

ST7263

I²C BUS INTERFACE (Cont’d)

5.7.5 Low Power Modes

Mode

WAIT

Description

No effect on I²C interface.

I²C interrupts exit from Wait mode.

I²C registers are frozen.

HALT

In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The I²C

interface resumes operation when the MCU is woken up by an interrupt with “exit from Halt

mode” capability.

5.7.6 Interrupts

Figure 41. Event Flags and Interrupt Generation

BTF

ITE

ADSL

SB

AF

STOPF

ARLO

BERR

*

* EVF can also be set by EV6 or an error from the SR2 register.

INTERRUPT

EVF

Interrupt Event

End of Byte Transfer Event

Address Matched Event (Slave mode)

Start Bit Generation Event (Master mode)

Acknowledge Failure Event

Stop Detection Event (Slave mode)

Arbitration Lost Event (Multimaster configuration)

Bus Error Event

The I²C interrupt events are connected to the

same interrupt vector (see Interrupts chapter).

Event

Flag

Enable

Control

Bit

BTF

ADSEL

SB

AF

ITE

STOPF

ARLO

BERR

Exit

from

Wait

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Exit

from

Halt

No

No

No

No

No

No

No

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC

register is reset (RIM instruction).

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