STM32F031G4U7TR 데이터 시트보기 (PDF) - STMicroelectronics
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STM32F031G4U7TR
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STM32F031G4U7TR Datasheet PDF : 106 Pages
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STM32F031x4 STM32F031x6
Electrical characteristics
6.3.6
Wakeup time from low-power mode
The wakeup times given in Table 30 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 18: General operating conditions..
Table 30. Low-power mode wakeup timings
Symbol
Parameter
Conditions
Typ @VDD = VDDA
= 2.0 V = 2.4 V = 2.7 V = 3 V
Max Unit
= 3.3 V
tWUSTOP
Wakeup from Stop
mode
Regulator in run
mode
Regulator in low
power mode
tWUSTANDBY
Wakeup from
Standby mode
-
tWUSLEEP
Wakeup from Sleep
mode
-
3.2
3.1
2.9
2.9
7.0
5.8
5.2
4.9
60.4 55.6 53.5
52
4 SYSCLK cycles
2.8 5
4.6 9
µs
51
-
-
6.3.7
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 14: High-speed external clock
source AC timing diagram.
Symbol
Table 31. High-speed external user clock characteristics
Parameter(1)
Min
Typ
Max
fHSE_ext User external clock source frequency
-
8
32
VHSEH OSC_IN input pin high level voltage
0.7 VDDIOx
-
VDDIOx
VHSEL OSC_IN input pin low level voltage
VSS
-
0.3 VDDIOx
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
15
-
-
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
-
-
20
Unit
MHz
V
ns
DocID025743 Rev 6
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