PSD814F2A-12MIT 데이터 시트보기 (PDF) - STMicroelectronics

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PSD814F2A-12MIT

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

AC/DC parameters

PSD8XXFX

Table 59. WRITE timing (3 V devices) (continued)

Symbol

Parameter

Conditions

-12

-15

-20

Unit

Min Max Min Max Min Max

tAVPV

tWLMV

Address input valid to address output delay

WR valid to port output valid using

macrocell register Preset/Clear

(5)

(2)(6)

33

35

40 ns

70

70

80 ns

1. Any input used to select an internal PSD function.

2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.

3. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

4. Assuming WRITE is active before data becomes valid.

5. In multiplexed mode, latched address generated from ADIO delay to address output on any port.

t(s) 6. Assuming data is stable before active WRITE signal.

uc Table 60. Program, WRITE and Erase times (5 V devices)

rod Symbol

Parameter

Min.

Typ.

Max.

P Flash Program

te Flash Bulk Erase (pre-programmed)(1)

8.5

3

30

le Flash Bulk Erase (not pre-programmed)

5

so tWHQV3

Ob tWHQV2

t(s) - tWHQV1

Sector Erase (pre-programmed)

Sector Erase (not pre-programmed)

Byte Program

Program/Erase cycles (per sector)

1

2.2

14

100,000

30

1200

c tWHWLO

du tQ7VQV

Sector Erase timeout

DQ7 valid to output (DQ7-DQ0) valid (data polling)(2)

100

30

ro 1. The whole memory is programmed to 00h before erase.

P 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Unit

s

s

s

s

s

µs

cycles

µs

ns

lete Table 61. Program, WRITE and Erase times (3 V devices)

so Symbol

Parameter

Min.

Ob Flash Program

Typ.

Max.

Unit

8.5

s

Flash Bulk Erase (pre-programmed)(1)

3

30

s

Flash Bulk Erase (not pre-programmed)

5

s

tWHQV3

tWHQV2

tWHQV1

Sector Erase (pre-programmed)

Sector Erase (not pre-programmed)

Byte Program

Program / Erase Cycles (per sector)

1

2.2

14

100,000

30

1200

s

s

µs

cycles

tWHWLO

tQ7VQV

Sector Erase timeout

DQ7 valid to Output (DQ7-DQ0) valid (data polling)(2)

100

µs

30

ns

110/128

Doc ID 7833 Rev 7

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