PSD814F3A-90UT 데이터 시트보기 (PDF) - STMicroelectronics
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PSD814F3A-90UT Datasheet PDF : 128 Pages
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PSD8XXFX
AC/DC parameters
Table 69. ISC timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min Max Min Max Min Max
tISCCF
Clock (TCK, PC1) frequency (except for
PLD)
(1)
12
10
9 MHz
tISCCH
Clock (TCK, PC1) high time (except for
PLD)
(1)
40
45
51
ns
tISCCL
Clock (TCK, PC1) low time (except for
PLD)
(1)
40
45
51
ns
tISCCFP Clock (TCK, PC1) frequency (PLD only)
(2)
) tISCCHP Clock (TCK, PC1) high time (PLD only)
(2)
t(s tISCCLP Clock (TCK, PC1) low time (PLD only)
(2)
c tISCPSU ISC port setup time
du tISCPH ISC port hold up time
ro tISCPCO ISC port clock to output
te P tISCPZV ISC port high-Impedance to valid Output
le tISCPVZ ISC port valid Output to high-Impedance
o 1. For non-PLD Programming, Erase or in ISC by-pass mode.
s 2. For program or erase PLD only.
2
2
2 MHz
240
240
240
ns
240
240
240
ns
12
13
15
ns
5
5
5
ns
30
36
40 ns
30
36
40 ns
30
36
40 ns
- Ob Table 70. Power-down timing (5 V devices)
t(s) Symbol
Parameter
Conditions
duc tLVDV
Pro tCLWH
ALE access time from Power-down
Maximum delay from APD Enable to
Internal PDN valid signal
te 1. tCLCL is the period of CLKIN (PD1).
Using CLKIN
(PD1)
-70
-90
-15
Unit
Min Max Min Max Min Max
80
90
150 ns
15 * tCLCL(1)
µs
Obsole Table 71. Power-down timing (3 V devices)
-12
-15
-20
Symbol
Parameter
Conditions
Unit
Min Max Min Max Min Max
tLVDV
tCLWH
ALE access time from Power-down
Maximum Delay from APD Enable to
Internal PDN valid Signal
Using CLKIN
(PD1)
145
150
15 * tCLCL(1)
200 ns
µs
1. tCLCL is the period of CLKIN (PD1).
Doc ID 7833 Rev 7
115/128
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