ST72F324J2TCRS 데이터 시트보기 (PDF) - STMicroelectronics

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ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Master mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

register and then shifted out serially to the MOSI pin most significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if the SPIE bit is set and the interrupt mask in the

CCR register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set.

2. A read to the SPIDR register.

Obsolete Product(s) - Obsolete Product(s) Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

register is read.

Slave mode operation

In slave mode, the serial clock is received on the SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the following actions:

– Select the clock polarity and clock phase by configuring the CPOL and CPHA bits

(see Figure 52). The slave must have the same CPOL and CPHA settings as the

master.

– Manage the SS pin as described in Slave Select management on page 100 and

Figure 50. If CPHA = 1, SS must be held low continuously. If CPHA = 0, SS must

be held low during byte transmission and pulled up between each byte to let the

slave write in the shift register.

2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI

I/O functions.

Slave mode transmit sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift

register and then shifted out serially to the MISO pin most significant bit first.

The transmit sequence begins when the slave device receives the clock signal and the most

significant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR

register is cleared.

Clearing the SPIF bit is performed by the following software sequence:

1. An access to the SPICSR register while the SPIF bit is set.

2. A write or a read to the SPIDR register.

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

register is read.

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Doc ID 13841 Rev 1

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