ST72F324J2TARS 데이터 시트보기 (PDF) - STMicroelectronics

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ST72F324J2TARS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

Supply, reset and clock management

6

Supply, reset and clock management

ST72324xx-Auto

6.1

Introduction

The device includes a range of utility features for securing the application in critical

situations (for example in case of a power brown-out), and reducing the number of external

components. An overview is shown in Figure 10.

For more details, refer to the dedicated parametric section.

Main features

● Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used

) with internal RC oscillator in order to respect the max. operating frequency)

t(s ● Multi-Oscillator clock management (MO)

c – 5 crystal/ceramic resonator oscillators

u – 1 Internal RC oscillator

rod ● Reset Sequence Manager (RSM)

P ● System Integrity management (SI)

te – Main supply low voltage detection (LVD)

le – Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

o supply

Obs 6.2

roduct(s) - Caution:

PLL (phase locked loop)

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to

multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option

byte. If the PLL is disabled, then fOSC2 = fOSC/2.

The PLL is not recommended for applications where timing accuracy is required.

Furthermore, it must not be used with the internal RC oscillator.

P Figure 9. PLL block diagram

Obsolete fOSC

PLL x 2

/2

0

fOSC2

1

PLL option bit

32/193

Doc ID 13841 Rev 1

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