CDB8952T-IQ 데이터 시트보기 (PDF) - Cirrus Logic
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CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Basic Mode Status Register - Address 01h (Cont.)
BIT
NAME
3
Auto-Neg Ability
2
Link Status
TYPE
Read Only 1
Read Only 0
RESET
1
Jabber Detect
Read Only 0
DESCRIPTION
This bit indicates that the CS8952T has auto-negotia-
tion capability. It will always read back a value of 1.
When set, this bit indicates that a valid link has been
established. Upon a link failure, this bit is cleared and
latched. It will remain cleared until this register is
read.
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set. If JabberiE (Inter-
rupt Mask Register (address 10h), bit 3) is set, an MII
Interrupt will be generated.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this register,
a read to the Interrupt Status Register (address 11h),
or a reset.
0
Extended Capability Read Only 1
No jabber detect function has been defined for
100BASE-TX.
This bit indicates that an extended register set may
be accessed (registers beyond address 01h). This bit
always reads back a value of 1.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
34
DS206TPP2
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