QL82SD-6PS484M 데이터 시트보기 (PDF) - QuickLogic Corporation
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QL82SD-6PS484M Datasheet PDF : 60 Pages
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QL82SD Device Data Sheet Rev C
pad_Ch0_p/n
Ch0_rxclk
Ch0_rxd[9:0]
t DD
t RXPD
A
B
Ch0_txclk
Figure 23: 10:1 Mode Deserializer Receive with Embedded Clock
2.0V
Enable
Chx_txclk
Pad_Chx_p/n
Chx_lock
t ZHLK
Chx-rxd
[N-1,0]
t DSR1
SYNC patterns
t ZHR or
t ZLR
Data
0.8V
1.5V
SYNC Symbol or DIN0-9
tHZR or tLZR
Chx_rxclk
OE
Figure 24: Deserializer PLL Lock Time from Power Down
VCC
Enable
0.8V
0.0V
Chx_txclk
Pad_Chx_p/n
Chx_lock
Chx-rxd
[N-1,0]
t DSR2
SYNC patterns
tZHR or
t ZLR
Data
1.2V
1.0V
SYNC Symbol or DIN0-9
t HZR or t LZR
Chx_rxclk
OE
Figure 25: 10:1 Mode Deserializer PLL Lock Time from SYNCPAT
© 2002 QuickLogic Corporation
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