ST72325J4T5(2007) 데이터 시트보기 (PDF) - STMicroelectronics

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ST72325J4T5
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the MCCSR register. It indicates when set

that the main oscillator has reached the selected

elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read / Write

Reset Value: 0000 0000 (00h)

7

0

0

0

0

0

0

0 BC1 BC0

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

BC1 BC0

Beep mode with fOSC2=8MHz

0

0

Off

0

1

1

0

1

1

~2-KHz

~1-KHz

~500-Hz

Output

Beep signal

~50% duty cycle

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the

consumption.

Table 16. Main Clock Controller Register Map and Reset Values

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

002Bh

SICSR

Reset Value

AVDS

0

AVDIE

0

AVDF LVDRF

0

x

0

CSSIE

0

CSSD WDGRF

0

x

002Ch

MCCSR

Reset Value

MCO

0

CP1

0

CP0

SMS

0

0

TB1

0

TB0

0

OIE

0

OIF

0

002Dh

MCCBCR

Reset Value

0

0

0

0

0

BC1

BC0

0

0

0

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