ST72325C9 데이터 시트보기 (PDF) - STMicroelectronics

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ST72325C9

8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE

STMicroelectronics 

ST72325

CLOCK CHARACTERISTICS (Cont’d)

12.5.5 Clock Security System (CSS)

Symbol

Parameter

fSFOSC

Safe Oscillator Frequency 1)

Conditions

Min

Typ

Max

Unit

3

MHz

Note:

1. Data based on characterization results.

12.5.6 PLL Characteristics

Symbol

fOSC

∆ fCPU/ fCPU

Parameter

PLL input frequency range

Instantaneous PLL jitter 1)

Conditions

fOSC = 4 MHz.

Min

Typ

Max

Unit

2

4

MHz

0.7

2

%

Note:

1. Data characterized but not tested.

The user must take the PLL jitter into account in the application (for example in serial communication or

sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several

CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the

PLL jitter.

Figure 78 shows the PLL jitter integrated on application signals in the range 125kHz to 4MHz. At frequen-

cies of less than 125KHz, the jitter is negligible.

Figure 78. Integrated PLL Jitter vs signal frequency1

+/-Jitter (%)

1.2

1

Max

Typ

0.8

0.6

0.4

0.2

0

4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz

Application Frequency

Note 1: Measurement conditions: fCPU = 8MHz.

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