CL-PS7500FE Просмотр технического описания (PDF) - Cirrus Logic
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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
The system software can then read the request registers to determine the sources that requested an inter-
rupt. Reading the status registers indicate the sources that requested interrupts, even if they were
masked.
The IRQA request register is slightly different in that some of the interrupt flags are edge triggered and
thus need to be cleared after they are read. All other request registers are read-only, but the IRQRQA
register can be written to clear triggered interrupts. A write of ‘1’ to a bit clears that interrupt. A write of ‘0’
causes no action to be taken.
Table 11-3. Interrupts
Register Bit Polarity/Type
Name/Function
FIQ
IRQA
IRQB
IRQC
7
Always active for software generated FIQ
6
Low
nINT8 interrupt pin
5
4
Low
nINT6 interrupt pin
3
2
1
High
INT5 interrupt pin
0
High
INT9 interrupt pin
7
Always active for software generated IRQ
6
Internal
2-MHz timer 1
5
Internal
2-MHz timer 0
4
Falling edge nPOR power on reset
3
Internal
Flyback from video subsystem
2
Falling edge nINT1 interrupt pin
1
0
Rising edge INT2 interrupt pin
7
Internal
Keyboard Rx buffer full
6
Internal
Keyboard Tx buffer empty
5
Low
nINT3 interrupt pin
4
Low
nINT4 interrupt pin
3
High
INT5 interrupt pin
2
Low
nINT6 interrupt pin
1
High
INT7 interrupt pin
0
Low
nINT8 interrupt pin
7
Low
IOP[7] interrupt pin
6
Low
IOP[6] interrupt pin
5
Low
IOP[5] interrupt pin
4
Low
IOP[4] interrupt pin
122
I/O SUBSYSTEMS
ADVANCE DATA BOOK v2.0
June 1997
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