CL-PS7500FE Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

производитель

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

13. SOUND FEATURES

13.1 Sound

The video and sound macrocell has a digital sound system. This is a 32-bit serial sound interface suitable

for driving external CD DACs.

13.2 The Sound FIFO

At the core of the sound system is a 4-word FIFO and a byte-wide latch. When empty, the FIFO fills com-

pletely by a DMA request. Data is then clocked out of the FIFO, one byte at a time, through the latch.

13.3 The Digital Serial Sound Interface

The serial sound interface offers a high quality 32-bit stereo sound, needing only a small amount of exter-

nal circuitry. The serial sound system consists of a three-pin serial interface:

q SDCLK is the Serial Data Clock output

q SDO is the Serial Data output

q WS is the Word Select output

When no sound is required (SCTL[2:1] = 0), these outputs are stable (SDCLK = 0, SDO = 0, WS = 1).

In this mode, bytes from the sound FIFO are output in most-significant-first order. This is because the

serial sound output must be MSB-first to be compatible with other serial sound devices. Each byte of data

is loaded into a parallel-in, serial-out register and clocked out under control of the bit clock.

13.3.1 Timing Formats

There are two timing formats available for the interface:

q Normal

q Japanese

This selection is controlled by bit 0 of the VIDMUX register in the main part of the CL-PS7500FE.

Normal Format

When configured for Normal mode (VIDMUX bit 0 = low), each 32-bit sample consists of 16 bits for the

left-hand channel and 16 bits for the right-hand channel. To distinguish between them, a WS signal is pro-

duced. This signal changes when the LSB of the previous word is output. When WS is high, the right-hand

channel is being output.

Japanese Format

In Japanese format, the WS signal changes when the MSB of the new word is output. In addition, the

polarity of WS is reversed.

The serial sound output can be used with any DAC with a serial sound input. Many DACs require a

11.2896-MHz input clock and, to reduce the required number of on-board crystals, the video and sound

macrocell can cope with this frequency on the SCLK input. When using this configuration, the following

parameters must be programmed in the registers:

June 1997

ADVANCE DATA BOOK v2.0

SOUND FEATURES

133

Share Link: