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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

22.5 System Reset Timing

Table 22-2. Reset Timing

Symbol Parameter

40 MHz

56 MHz

MIN MAX MIN MAX

Units

t pr

Time for which nPOR must be held low to guarantee a reset

20

20

ns

tpre a

Length of internal reset

2

4

2

4

µs

tnrb, c

Time for which nRESET must be held low to guarantee reset

2

2

µs

trec

Length of internal reset

2

2

µs

tres

nRESET setup to I_OCLK rising

0

0

ns

treh

nRESET hold from I_OCLK rising

30

30

ns

a tpre = 2 µs if I_OCLK is 64 MHz. tpre is 32 MHz; this reset forces Divide-by-2 mode on the clock inputs.

b DMA or writes from the ARM processor prevent nRESET having any effect for their duration. Thus the ‘soft’ reset cannot

break write cycles or cause partial DRAM refresh.

c Assuming IOCK32 is 32 MHz.

nPOR

tp r

nRESET

RESET

tp r e

nRESET

RESET

tn r

tr e

I_OCLK

nRESET

tr e s

tr e h

Figure 22-1. System Reset Timing

200

ELECTRICAL SPECIFICATIONS

ADVANCE DATA BOOK v2.0

June 1997

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