STM32F103VC Просмотр технического описания (PDF) - STMicroelectronics

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STM32F103VC

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

STMicroelectronics 

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK)

tw(CLK)

BUSTURN = 0

FSMC_CLK

td(CLKL-NExL)

FSMC_NEx

Data latency = 1

td(CLKH-NExH)

td(CLKL-NADVL)

FSMC_NADV

td(CLKL-NADVH)

FSMC_A[25:0]

td(CLKL-AV)

td(CLKH-AIV)

FSMC_NOE

FSMC_D[15:0]

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

td(CLKL-NOEL)

td(CLKH-NOEH)

tsu(DV-CLKH)

tsu(NWAITV-CLKH)

th(CLKH-DV)

tsu(DV-CLKH)

D1

D2

th(CLKH-DV)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

ai14894d

Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)

Symbol

Parameter

Min

Max Unit

tw(CLK)

FSMC_CLK period

27.7

ns

td(CLKL-NExL)

FSMC_CLK low to FSMC_NEx low (x = 0...2)

1.5

ns

td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x = 0...2) THCLK + 2

ns

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

4

ns

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

5

ns

td(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x = 0...25)

0

ns

td(CLKH-AIV)

FSMC_CLK high to FSMC_Ax invalid (x = 0...25) THCLK + 4

ns

td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low

THCLK + 1.5 ns

td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high

THCLK + 1.5

ns

tsu(DV-CLKH)

FSMC_D[15:0] valid data before FSMC_CLK high 6.5

ns

th(CLKH-DV)

FSMC_D[15:0] valid data after FSMC_CLK high 7

ns

tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high 7

ns

th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high

2

ns

1. CL = 15 pF.

2. Based on characterization, not tested in production.

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Doc ID 14611 Rev 7

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