Z80230 Просмотр технического описания (PDF) - Zilog

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Z80230

Zilog SCC Serial Communication Controller

Zilog 

Application Note

Interfacing Z80® CPUs to the Z8500 Peripheral Family

6

Figure 1. Z8500 Peripheral I/O Read Cycle Timing

Write Cycle Timing

Figure 2 illustrates the Z8500 Write cycle timing. All

register addresses and /INTACK must remain stable

throughout the cycle. If /CE goes active after /WR goes

active, or if /CE goes inactive before /WR goes inactive,

then the effective Write cycle is shortened. Data must be

available to the peripheral prior to the falling edge of /WR.

Figure 2. Z8500 Peripheral I/O Write Cycle Timing

UM010901-0601

6-3

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