CS61310(2003) Просмотр технического описания (PDF) - Cirrus Logic
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CS61310 Datasheet PDF : 30 Pages
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CS61310
An address/command byte, shown in Figure 10,
points to addresses 0x10 through 0x15 (address
0x10 shown), and precedes a data byte. The first
bit of the address/command byte determines
whether a read or a write is requested. The next six
bits contain the address. The last bit is ignored.
Data to the internal registers is input on the eight
clock cycles immediately following the ad-
dress/command byte.
CS
SCLK
SDI
SDO
CLKE = 0
R/W 0 0 0 0 1 0 0 D0 D1 D2 D3 D4 D5 D6 D7
Address/Command Byte
D ata Input/O utput
D0 D1 D2 D3 D4 D5 D6 D7
Figure 10. Input/Output Timing (showing address 0x10)
7
Control Register 1
(CR1)
Control Register 2
(CR2)
Equalizer Gain
(EQGAIN)
RAM Address
(RAM)
Reserved
Set to “0”
TAOS
AIS
X
MSB
0
6
5
4
3
LLOOP RLOOP LB02
LB01
RAMPLSE
RSVD
set to “0”
LOOPDN
LOOPUP
X
X
EQ4
EQ3
-
-
-
-
0
0
0
0
2
CODER
TAZ
RPWDN
EQ2
-
0
1
NLOOP
TxHIZ
EQ1
-
0
0
ADDR
LOS 0x10 R/W
RSVD
set to “0”
0x11 R/W
EQ0 0x12 R
LSB 0x13 R/W
0
0x14
Table 3. Register Map
DS440F1 FEB ‘03
13
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