DSPIC30F2013AT-30IML Просмотр технического описания (PDF) - Microchip Technology

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DSPIC30F2013AT-30IML

High-Performance, 16-Bit Digital Signal Controllers

Microchip Technology 

dsPIC30F3014/4013

TABLE 23-28: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.5V to 5.5V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic(1)

Min

Typ(2) Max

Units

Conditions

CS10 TcSCKL CSCK Input Low Time

TCY/2 + 20 —

—

ns

—

(CSCK pin is an input)

CSCK Output Low Time(3)

30

—

—

ns

—

(CSCK pin is an output)

CS11 TcSCKH CSCK Input High Time

TCY/2 + 20 —

—

ns

—

(CSCK pin is an input)

CSCK Output High Time(3)

30

—

—

ns

—

(CSCK pin is an output)

CS20 TcSCKF CSCK Output Fall Time(4)

—

10

25

ns

—

(CSCK pin is an output)

CS21 TcSCKR CSCK Output Rise Time(4)

—

10

25

ns

—

(CSCK pin is an output)

CS30 TcSDOF CSDO Data Output Fall Time(4)

—

10

25

ns

—

CS31 TcSDOR CSDO Data Output Rise Time(4)

—

10

25

ns

—

CS35 TDV

Clock edge to CSDO data valid

—

—

10

ns

—

CS36 TDIV

Clock edge to CSDO tri-stated

10

—

20

ns

—

CS40 TCSDI

Setup time of CSDI data input to

20

—

—

ns

—

CSCK edge (CSCK pin is input

or output)

CS41 THCSDI Hold time of CSDI data input to

20

—

—

ns

—

CSCK edge (CSCK pin is input

or output)

CS50 TcoFSF

COFS Fall Time

(COFS pin is output)

—

10

25

ns Note 1

CS51 TcoFSR

COFS Rise Time

(COFS pin is output)

—

10

25

ns Note 1

CS55 TscoFS Setup time of COFS data input to

20

—

—

ns

—

CSCK edge (COFS pin is input)

CS56 THCOFS Hold time of COFS data input to

20

—

—

ns

—

CSCK edge (COFS pin is input)

CS57 TPCSCK CSCK clock period

100

—

—

ns

—

Note 1:

2:

3:

4:

These parameters are characterized but not tested in manufacturing.

Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

Assumes 50 pF load on all DCI pins.

DS70138E-page 186

© 2007 Microchip Technology Inc.

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