M95160-FDW6P(2014) Просмотр технического описания (PDF) - STMicroelectronics
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M95160-FDW6P Datasheet PDF : 47 Pages
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DC and AC parameters
M95160 M95160-W M95160-R M95160-DF
Table 17. AC characteristics (M95160-W, device grade 6)
Test conditions specified in Table 8 and Table 11
Symbol Alt.
Parameter
(1)
VCC = 2.5 to 5.5 V VCC = 4.5 to 5.5 V Unit
Min. Max. Min. Max.
fC
fSCK Clock frequency
D.C.
10
D.C.
20 MHz
tSLCH tCSS1 S active setup time
30
-
15
-
ns
tSHCH tCSS2 S not active setup time
30
-
15
-
ns
tSHSL
tCS S deselect time
40
-
20
-
ns
tCHSH tCSH S active hold time
30
-
15
-
ns
tCHSL
tCH(2)
tCL(2)
tCLCH(3)
tCHCL(3)
S not active hold time
tCLH Clock high time
tCLL Clock low time
tRC Clock rise time
tFC Clock fall time
30
-
15
-
ns
40
-
20
-
ns
40
-
20
-
ns
-
2
-
2
µs
-
2
-
2
µs
tDVCH tDSU Data in setup time
10
-
5
-
ns
tCHDX
tDH Data in hold time
10
-
10
-
ns
tHHCH
Clock low hold time after HOLD not active
30
-
15
-
ns
tHLCH
Clock low hold time after HOLD active
30
-
15
-
ns
tCLHL
Clock low set-up time before HOLD active
0
-
0
-
ns
tCLHH
Clock low set-up time before HOLD not active 0
-
0
ns
tSHQZ(3) tDIS Output disable time
-
40
-
20
ns
tCLQV(4)
tV Clock low to output valid
-
40
-
20
ns
tCLQX
tQLQH(3)
tQHQL(3)
tHO Output hold time
tRO Output rise time
tFO Output fall time
0
-
0
-
ns
-
40
-
20
ns
-
40
-
20
ns
tHHQV
tHLQZ(3)
tLZ HOLD high to output valid
tHZ HOLD low to output high-Z
-
40
-
20
ns
-
40
-
20
ns
tW
tWC Write time
-
5
-
5
ms
1. Only for devices identified by process letter K.
2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
3. Characterized only, not tested in production.
4. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.
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DocID022580 Rev 5
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