LFSCM3GA40E-6F256I Просмотр технического описания (PDF) - Lattice Semiconductor

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LFSCM3GA40E-6F256I

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor

LFSCM3GA40E-6F256I Datasheet PDF : 237 Pages

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Lattice Semiconductor

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

PURESPEED I/O Recommended Operating Conditions

Standard

Min.

VCCIO (V)

Typ.

Max.

LVCMOS 33

3.135

3.3

3.465

LVCMOS 25

2.375

2.5

2.625

LVCMOS 18

1.71

1.8

1.89

LVCMOS 15

1.425

1.5

1.575

LVCMOS 12

1.14

1.2

1.26

LVTTL

3.135

3.3

3.465

PCI33

3.135

3.3

3.465

PCIX33

3.135

3.3

3.465

PCIX15

1.425

1.5

1.575

AGP1X33

3.135

3.3

3.465

AGP2X33

3.135

3.3

3.465

SSTL18_I, II3

1.71

1.8

1.89

SSTL25_I, II3

2.375

2.5

2.625

SSTL33_I, II3

3.135

3.3

3.465

HSTL15_I, II3

1.425

1.5

1.575

HSTL15_III1, 3 and IV1, 3

1.425

1.5

1.575

HSTL 18_I3, II3

1.71

1.8

1.89

HSTL 18_ III1, 3, IV1, 3

1.71

1.8

1.89

GTL121, 3, GTLPLUS151, 3

—

LVDS

—

Mini-LVDS

—

RSDS

—

HYPT (Hyper Transport)

—

LVPECL33 (outputs)2

3.135

3.3

3.465

LVPECL33 (inputs)2, 4

—

≤ 2.5

—

BLVDS252, 3

2.375

2.5

2.625

MLVDS252, 3

2.375

2.5

2.625

SSTL18D_I3, II3

1.71

1.8

1.89

SSTL25D_I3, II3

2.375

2.5

2.625

SSTL33D_I3, II3

3.135

3.3

3.465

HSTL15D_I3, II3

1.425

1.5

1.575

HSTL18D_I3, II3

1.71

1.8

1.89

1. Input only.

2. Inputs on chip. Outputs are implemented with the addition of external resisters.

3. Input for this standard does not depend on the value of VCCIO.

4. Inputs for this standard cannot be in 3.3V VCCIO banks (≤ 2.5V only).

Min.

—

0.49VCCIO

—

0.39VCCIO

0.833

1.15

1.3

0.68

0.816

0.882

—

VREF (V)

Typ.

—

0.5VCCIO

—

0.4VCCIO

0.9

1.25

1.5

0.75

0.9

1.08

1.0

—

Max.

—

0.51VCCIO

—

0.41VCCIO

0.969

1.35

1.7

0.9

1.08

1.122

—

3-4

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