STM32F302CC Просмотр технического описания (PDF) - STMicroelectronics

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STM32F302CC

ARM®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+ 40KB SRAM, 2 ADCs, 1 DAC ch., 4 comp, 2 PGA, timers, 2.0-3.6 V

STMicroelectronics 

STM32F302xB STM32F302xC

Electrical characteristics

6.3.4

Embedded reference voltage

The parameters given in Table 28 are derived from tests performed under ambient

temperature and VDD supply voltage conditions summarized in Table 24.

Symbol

Table 28. Embedded internal reference voltage

Parameter

Conditions

Min Typ Max Unit

VREFINT

TS_vrefint

Internal reference voltage –40 °C < TA < +105 °C 1.2

–40 °C < TA < +85 °C 1.2

ADC sampling time when

reading the internal

-

2.2

reference voltage

Internal reference voltage

VRERINT

spread over the

temperature range

VDD = 3 V ±10 mV

-

TCoeff

Temperature coefficient

-

-

1. Guaranteed by characterization results.

2. Guaranteed by design.

1.23 1.25

V

1.23 1.24(1) V

-

-

µs

-

10(2)

mV

- 100(2) ppm/°C

Table 29. Internal reference voltage calibration values

Calibration value name

Description

Memory address

VREFINT_CAL

Raw data acquired at

temperature of 30 °C

VDDA= 3.3 V

0x1FFF F7BA - 0x1FFF F7BB

6.3.5

Supply current characteristics

The current consumption is a function of several parameters and factors such as the

operating voltage, ambient temperature, I/O pin loading, device software configuration,

operating frequencies, I/O pin switching rate, program location in memory and executed

binary code.

The current consumption is measured as described in Figure 12: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a

reduced code that gives a consumption equivalent to CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in input mode with a static value at VDD or VSS (no load)

• All peripherals are disabled except when explicitly mentioned

• The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0

to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)

• Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)

• When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2

• When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or

HSE (8 MHz) in bypass mode.

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