PSD4233F2V-20UI Просмотр технического описания (PDF) - STMicroelectronics

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PSD4233F2V-20UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

Figure 31. Port E, F and G Structure

WR

ADDRESS

ALE

DATA OUT

Register

DQ

DQ

G

Ext. CS (Port F)

READ MUX

P

D

B

DATA OUT

ADDRESS

A[ 7:0] OR A[15:8]

DATA IN

CONTROL Register

DQ

WR

DIR Register

DQ

WR

ENABLE PRODUCT TERM (.OE)

CPLD - INPUT (Port F)

OUTPUT

MUX

OUTPUT

SELECT

ENABLE OUT

PORT Pin

ISP or Battery Back-Up (Port E)

Configuration Bit

Port F – Functionality and Structure

Port F can be configured to perform one or more

of the following functions:

s MCU I/O Mode

s CPLD Output – External Chip Select (ECS7-

ECS0) can be connected to Port F or Port C.

s CPLD Input – direct input to the CPLD, no Input

Macrocells (IMC)

s Latched Address output – Provide latched

address output as per Table 41.

s Slew Rate – pins can be configured for fast Slew

Rate

s Data Port – connected to D7-D0 when Port F is

configured as Data Port for a non-multiplexed

bus

s Peripheral Mode

AI04938

s MCU Reset Mode – for 16-bit Motorola 683xx

and HC16 MCUs

Port G – Functionality and Structure

Port G can be configured to perform one or more

of the following functions:

s MCU I/O Mode

s Latched Address output – Provide latched

address output as per Table 41.

s Open Drain – pins can be configured in Open

Drain Mode

s Data Port – connected to D15-D8 when Port G

is configured as Data Port for a non-multiplexed

bus

s MCU Reset Mode – for 16-bit Motorola 683xx

and HC16 MCUs

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