PSD412A2-C-90UI 查看數據表（PDF） - STMicroelectronics
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PSD412A2-C-90UI Datasheet PDF : 123 Pages
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The PSD4XX
Architecture
(cont.)
PSD4XX Family
Table 18. Power Management Mode Registers (PMMR0, PMMR1)
PMMR0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR CLK ZPLD
RCLK
ZPLD
ACLK
ZPLD
TURBO
CMISER
APD
ENABLE
ALE PD
Polarity
*
1 = OFF 1 = OFF 1 = OFF 1 = OFF 1 = ON 1 = ON 1 = HIGH
Bit 0 * = Should be set to High (1) to operate the APD.
Bit 1 0 = ALE Power Down (PD) Polarity Low.
1 = ALE Power Down (PD) Polarity High.
Bit 2 0 = Automatic Power Down (APD) Disable.
1 = Automatic Power Down (APD) Enable.
Bit 3 0 = EPROM/SRAM CMiser is OFF.
1 = EPROM/SRAM CMiser is ON.
Bit 4 0 = ZPLD Turbo is ON. ZPLD is always ON.
1 = ZPLD Turbo is OFF. ZPLD will Power Down when inputs are not changing.
Bit 5 0 = ZPLD Clock Input into the Array from the CLKIN pin input is connected.
Every Clock change will Power Up the ZPLD when Turbo bit is OFF.
1 = ZPLD Clock Input into the Array from the CLKIN pin input is disconnected.
Bit 6 0 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is connected.
1 = ZPLD Clock Input into the the MacroCell registers from the CLKIN pin input
is disconnected.
Bit 7 * = In the PSD4XX should be set to High (1)
PMMR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sleep APD CLK
*
*
*
*
*
*
Mode
1 = ON 1 = CLKIN
Bit 0
0 = Automatic Power Down Unit Clock is connected to Port E7 (PE7) alternate
function input.
1 = Automatic Power Down Unit Clock is connected to the PSD Clock
input (CLKIN).
Bit 1 0 = Sleep Mode Disabled.
1 = Sleep Mode Enabled.
Bit 2–7 0 = Reserved for future use, should be set to zero.
Table 19. APD Counter Operation
APD EN Bit
ALE Power
Down Polarity
0
X
1
X
1
1
1
0
ALE Status
X
Pulsing
1
0
APD Counter
Not Counting
Not Counting
Counting (Activates Standby
Mode After 15 Clocks)
Counting (Activates Standby
Mode After 15 Clocks)
69
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