PSD412A2-C-90UI 查看數據表（PDF） - STMicroelectronics
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PSD412A2-C-90UI Datasheet PDF : 123 Pages
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PSD4XX Family
13.10 AC/DC Parameters – ZPLD Timing Parameters (ZPSD4XXV Versions)
(3.0 V ± 10%)
Combinatorial Delays (3.0 V ± 10%)
Symbol
Parameter
Conditions
-20
-25
ZPLD_TURBO
Min Max Min Max OFF*
Unit
t PD
t RPD
t EA
t ER
t ARP
t ARPW
t ARD
I/O Input or Feedback to
Combinatorial Output
Registered Input to
Combinatorial Output
Input to Output Enable
Input to Output Disable
Register Clear or Preset Delay
Register Clear or Preset
Pulse Width
Array Delay
Port B, E
55
80
Add 20
ns
(Note 1)
55
85
Add 20
ns
Any Input
Any Input
Any Input
50
80
Add 20
ns
50
80
Add 20
ns
55
80
Add 20
ns
Any Input
30
60
ns
33
35
ns
NOTE: 1. Port A and latched address from ADIO (A0, A1, A8 – A15).
Synchronous Clock Mode (3.0 V ± 10%)
Symbol
Parameter
Conditions
-20
-25
ZPLD_TURBO
Min Max Min Max
OFF*
Unit
Maximum Frequency
External Feedback
1/(tS + tCO)
28.57
11.11
f MAX
tS
tH
t CH
t CL
t CO
t ARD
t MIN
Maximum Frequency
Internal Feedback (fCNT)
Maximum Frequency
Pipelined Data
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
Array Delay for Product
Term Expansion
Minimum Clock Period
1/(tS + tCO –10)
1/(tCH + tCL)
Any Input
Any Input
Clock Input
Clock Input
Clock Input
Any Macrocell
t CH + t CL
17.24
12.50
31.25
18.52
45
60
0
0
16
27
16
27
30
33
24
35
30
30
Add 20
0
0
0
0
0
0
*NOTE: If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
89
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