PIC18F010T-I/SN 查看數據表（PDF） - Microchip Technology
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PIC18F010T-I/SN Datasheet PDF : 176 Pages
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PIC18F010/020
ADDWFC
ADD WREG and Carry bit to f
Syntax:
[ label ] ADDWFC f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(WREG) + (f) + (C) → dest
Status Affected: N,OV, C, DC, Z
Encoding:
0010 00da ffff ffff
Description:
Add WREG, the Carry Flag and data
memory location ’f’. If ’d’ is 0, the
result is placed in WREG. If ’d’ is 1,
the result is placed in data memory
location 'f'. If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
Example:
ADDWFC
Before Instruction
C
=1
REG = 0x02
WREG = 0x4D
N
=?
OV
=?
DC
=?
Z
=?
REG, W
After Instruction
C
=
REG =
WREG =
N
=
OV
=
DC
=
Z
=
0
0x02
0x50
0
0
0
0
ANDLW
AND literal with WREG
Syntax:
[ label ] ANDLW k
Operands:
0 ≤ k ≤ 255
Operation:
(WREG) .AND. k → WREG
Status Affected: N,Z
Encoding:
0000 1011 kkkk kkkk
Description:
The contents of WREG are AND’ed
with the 8-bit literal 'k'. The result is
placed in WREG.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read literal
’k’
Q3
Process
Data
Q4
Write to
WREG
Example:
ANDLW
Before Instruction
WREG = 0xA3
N
=?
Z
=?
After Instruction
WREG =
N
=
Z
=
0x03
0
0
0x5F
DS41142A-page 102
Preliminary
2001 Microchip Technology Inc.
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