PIC18F010T-I/SN 查看數據表（PDF） - Microchip Technology
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PIC18F010T-I/SN Datasheet PDF : 176 Pages
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PIC18F010/020
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR literal with WREG
[ label ] IORLW k
0 ≤ k ≤ 255
(WREG) .OR. k → WREG
N,Z
0000 1001 kkkk kkkk
The contents of WREG are OR’ed
with the eight bit literal 'k'. The
result is placed in WREG.
1
1
Q2
Read
literal ’k’
Q3
Process
Data
Q4
Write to
WREG
Example:
IORLW
Before Instruction
WREG = 0x9A
N
=?
Z
=?
After Instruction
WREG =
N
=
Z
=
0xBF
1
0
0x35
IORWF
Inclusive OR WREG with f
Syntax:
[ label ] IORWF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(WREG) .OR. (f) → dest
Status Affected: N,Z
Encoding:
0001 00da ffff ffff
Description:
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ’f’
Q3
Process
Data
Q4
Write to
destination
Example:
IORWF RESULT, W
Before Instruction
RESULT = 0x13
WREG = 0x91
N
=?
Z
=?
After Instruction
RESULT =
WREG =
N
=
Z
=
0x13
0x93
1
0
DS41142A-page 118
Preliminary
2001 Microchip Technology Inc.
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