PIC18F010T-I/SN 查看數據表（PDF） - Microchip Technology

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PIC18F010T-I/SN

High Performance Microcontrollers

Microchip Technology 

PIC18F010/020

12.4 Secured Access Registers

This device contains programming options for safety

critical peripherals. Because these safety critical

peripherals can be programmed in software, the regis-

ters used to control these peripherals should be given

limited access by the user’s code. This way, errant

code won’t accidentally change settings in peripherals

that could cause catastrophic results.

The registers that are considered safety critical are the

Watchdog Timer Control register (WDTCON), the Low

Voltage Detect register (LVDTCON), and the Oscillator

Control register (OSCCON).

12.4.1 COMBINATION LOCK MODULE

Access is limited to using the Combination Lock

module.

Two bits called Combination Lock (CMLK) bits are

located in the lower two bits of the PSPCON register.

These two bits, and only these two bits, must be set in

sequence by the user’s code.

The Combination Lock bits must be set sequentially,

meaning that as soon as Combination Lock bit 1 is set,

the second Combination Lock bit must be set on the

following instruction cycle. If the user waits more than

one machine cycle to set the second bit after setting the

first, both bits will automatically be cleared in hardware,

and the lock will remain closed.

Each instruction must only modify one combination

lock bit at a time. This means that the first write to the

register will write the CMLK1 to a ’1’, but CMLK0 will

equal ’0’. The second write will only modify CMLK0.

This means that the data written to the PSPCON regis-

ter will have CMLK1 set to a ’1’ and CMLK0 set to a ’1’.

This leaves CMLK1 unmodified. This will restrict at

least one of the instructions used to modify this register

to a BSF of the PSPCON register. This will restrict the

combination of instructions that will allow the lock to be

opened, so that random code execution in the event of

a software fault, will not cause the lock to be acciden-

tally opened. The BSF instruction limitation will also

prevent random code from setting both bits at the same

time via a MOVWF instruction, since they are located in

the same register.

Note:

The Combination lock bits are write only

bits. These bits will always return ‘0’ when

read.

When each bit is set and the combination lock is

opened, the user will have three instruction cycles to

modify the safety critical register of his choice. After

three cycles have expired, the CMLK bits are cleared,

the lock will close, and the user will have to set the

CMLK bits in sequence again, in order to open the lock.

Thus, for each attempt to modify a safety critical regis-

ter, the combination lock must be opened before the

register can be written to. The reason that three instruc-

tion cycles were chosen for the unlock time was to

allow the user to put the "unlock" code in a subroutine

call. This way, the user’s code will only have one

instance of the code that is used to unlock the module.

The user would first set up the WREG register with the

desired data to load into a secured register, then call a

subroutine that contains the two BSF instructions, return

from the routine, and modify the secured register.

;Setup WREG with data to be stored

; in a safety critical register

MAIN

MOVLW 0x5A

CALL UNLOCK

;Write must take place on next

;instruction cycle

MOVWF OSCCON, 0

.

.

.

UNLOCK

BSF

PSPCON, CMLK1, 0

BSF

PSPCON, CMLK0, 0

RETURN

DS41142A-page 92

Preliminary

 2001 Microchip Technology Inc.

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