PIC16C925/926
FIGURE 15-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
I/O Pins
Note: Refer to Figure 15-4 for load conditions.
30
34
31
34
TABLE 15-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Symbol
Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
—
—
µs
31
TWDT Watchdog Timer Time-out Period
7
18
33 ms VDD = 5V, -40°C to +85°C
(No Prescaler)
32
TOST
Oscillation Start-up Timer Period
— 1024TOSC —
— TOSC = OSC1 period
33
TPWRT Power-up Timer Period
28
72
132 ms VDD = 5V, -40°C to +85°C
34
TIOZ
I/O Hi-impedance from MCLR Low —
—
2.1 µs
or Watchdog Timer Reset
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2001 Microchip Technology Inc.
Preliminary
DS39544A-page 149