PIC16LC925T-I/CL 查看數據表（PDF） - Microchip Technology

零件编号

产品描述 (功能)

生产厂家

PIC16LC925T-I/CL

64/68-Pin CMOS Microcontrollers with LCD Driver

Microchip Technology 

PIC16C925/926

FIGURE 15-15: I2C BUS DATA TIMING

SCL

SDA

In

103

90

91

100

101

106

107

109

109

SDA

Out

Note: Refer to Figure 15-4 for load conditions.

102

92

110

TABLE 15-10: I2C BUS DATA REQUIREMENTS

Parameter

No.

Symbol

Characteristic

Min

Max Units

Conditions

100

THIGH Clock high time 100 kHz mode

4.0

— µs Device must operate at a

minimum of 1.5 MHz

SSP Module

1.5TCY

—

101

TLOW

Clock low time

100 kHz mode

4.7

— µs Device must operate at a

minimum of 1.5 MHz

SSP Module

1.5TCY

—

102

TR

SDA and SCL rise 100 kHz mode

—

1000 ns

time

103

TF

SDA and SCL fall 100 kHz mode

—

300 ns

time

90

TSU:STA START condition 100 kHz mode

4.7

— µs Only relevant for Repeated

setup time

START condition

91

THD:STA START condition 100 kHz mode

4.0

— µs After this period the first

hold time

clock pulse is generated

106

THD:DAT Data input hold 100 kHz mode

0

— ns

time

107

TSU:DAT Data input setup 100 kHz mode

250

— ns

time

92

TSU:STO STOP condition 100 kHz mode

4.7

— µs

setup time

109

TAA

Output valid from 100 kHz mode

—

3500 ns (Note 1)

clock

110

TBUF

Bus free time

100 kHz mode

4.7

— µs Time the bus must be free

before a new transmission

can start

D102

CB

Bus capacitive loading

—

400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

DS39544A-page 156

Preliminary

 2001 Microchip Technology Inc.

Share Link: