ST62T08BN3/SWD 查看數據表（PDF） - STMicroelectronics

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ST62T08BN3/SWD

8-BIT MCUs WITH A/D CONVERTER, TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RESET

STMicroelectronics 

ST6208C/ST6209C/ST6210C/ST6220C

A/D CONVERTER (Cont’d)

9.3.5 Low power modes

Mode

WAIT

STOP

Description

No effect on A/D Converter. ADC interrupts

cause the device to exit from Wait mode.

A/D Converter disabled.

Note: The A/D converter may be disabled by clear-

ing the PDS bit. This feature allows reduced power

consumption when no conversion is needed.

9.3.6 Interrupts

Interrupt Event

Event

Flag

Enable

Bit

End of Conver-

sion

EOC

EAI

Exit

from

Wait

Yes

Exit

from

Stop

No

Note: The EOC bit is cleared only when a new

conversion is started (it cannot be cleared by writ-

ing 0). To avoid generating further EOC interrupt,

the EAI bit has to be cleared within the ADC inter-

rupt subroutine.

9.3.7 Register description

A/D CONVERTER CONTROL REGISTER (AD-

CR)

Address: 0D0h - Read/Write (Bit 6 Read Only, Bit

5 Write Only)

Reset value: 01000 0000 (40h)

7

0

EAI EOC STA PDS

D3

OSC

OF F

D1

D0

Bit 7 = EAI Enable A/D Interrupt.

0: ADC interrupt disabled

1: ADC interrupt enabled

Bit 6 = EOC End of conversion. Read Only

When a conversion has been completed, this bit is

set by hardware and an interrupt request is gener-

ated if the EAI bit is set. The EOC bit is automati-

Table 16. ADC Register Map and Reset Values

cally cleared when the STA bit is set. Data in the

data conversion register are valid only when this

bit is set to “1”.

0: Conversion is not complete

1: Conversion can be read from the DR register

Bit 5 = STA: Start of Conversion. Write Only.

0: No effect

1: Start conversion

Note: Setting this bit automatically clears the EOC

bit. If the bit is set again when a conversion is in

progress, the present conversion is stopped and a

new one will take place. This bit is write only, any

attempt to read it will show a logical zero.

Bit 4 = PDS Power Down Selection.

0: A/D converter is switched off

1: A/D converter is switched on

Bit 3 = D3 Not used, must be kept cleared.

Bit 2 = OSCOFF Main Oscillator off.

0: Main Oscillator enabled

1: Main Oscillator disabled

Note: This bit does not apply to the ADC peripher-

al but to the main clock system. Refer to the Clock

System section.

Bit 1:0 = D[1:0] Not used, must be kept cleared.

A/D CONVERTER DATA REGISTER (ADR)

Address: 0D1h - Read only

Reset value: xxh

7

0

D7 D6 D5 D4 D3 D2 D1 D0

Bit 7:0 = D[7:0]: 8 Bit A/D Conversion Result.

Address

(Hex.)

Register

Label

7

6

5

4

3

2

1

0

0D0h

ADR

Reset Value

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

0D1h

ADCR

Reset Value

EAI

0

EOC

STA

1

0

PDS

0

D3

0

D2

0

D1

0

D0

0

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