Z8018533FSC 查看數據表（PDF） - Zilog

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Z8018533FSC

SMART PERIPHERAL CONTROLLERS

Zilog 

Zilog

BCR0L

Read/Write

BC7

PRELIMINARY

Addr 26H

BC0

MAR1L

Read/Write

MA7

Z80185/Z80195

SMART PERIPHERAL CONTROLLERS

Addr 28H

MA0

BCR0H

Read/Write

BC15

Addr 27H

BC8

MAR1H

Read/Write

MA15

Addr 29H

MA8

Figure 49. DMA 0 Byte Counter Registers

MAR1B

Read/Write

Addr 2AH

MA19 MA16

----

Figure 50. DMA 1 Memory Address Registers

IAR1B

Addr 2D

D7 D6 D5 D4 D3 D2 D1 D0

New Z8S180 Register

000 = DMA1 ext TOUT/DREQ

001 = DMA1 ASCI0

010 = DMA1 ASCI1

011 = DMA1 ESCC

111 = DMA1 PIA27-20 (P1284)

0 = TOUT//DREQ is DREQ In

1 = TOUT//DREQ is TOUT Out

Reserved, program as 0.

Currently selected DMA

Channel when Bit 7 = 1

Alternating Channels

0 = DMA Channels

are independent

1 = Toggle between DMA

channels for same device

Figure 51. DMA I/O Address Register Ch. 1

46

DS971850301

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