STPCI2(2002) 查看數據表（PDF） - STMicroelectronics
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STPCI2 Datasheet PDF : 111 Pages
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DESIGN GUIDELINES
Check:
How?
Troubleshooting
3
SYSRSTI# Measure SYSRSTI# of STPC
(Power Good) See Figure 4-3 for waveforms.
Verify reset generation circuit:
- device reference
- components value
Measure HCLK is at selected frequency
5
HCLK
25MHz < HCLK < 66MHz
HCLK wire must be as short as possible
Measure PCICLKO:
- maximum is 33MHz by standard
Verify PCICLKO loops to PCICLKI.
6
PCI clocks
- check it is at selected frequency
Verify maximum skew between any PCI clock
- it is generated from HCLK by a division branch is below 2ns.
(1/2, 1/3 or 1/4)
In Synchronous mode, check MCLKI.
Check PCICLKI equals PCICLKO
Measure MCLKO:
- use a low-capacitance probe
7
Memory
clocks
- maximum is 90MHz
- check it is at selected frequency
- In SYNC mode MCLK=HCLK
Verify load on MCLKI.
Verify MCLK programming (BIOS setting).
- in ASYNC mode, default is 66MHz
Check MCLKI equals MCLKO
Measure SYSRSTO# of STPC
4
SYSRSTO# See Figure 4-3 for waveforms.
Verify SYSRSTI# duration.
Verify SYSRSTI# has no glitch
Verify clocks are running.
Check PCI signals are toggling:
- FRAME#, IRDY#, TRDY#, DEVSEL# Verify PCI slots
- these signals are active low.
If the STPC don’t boot
8a
PCI cycles
Check, with a logic analyzer, that first
- verify data read from boot memory is OK
PCI cycles are the expected ones:
- ensure Flash is correctly programmed
memory read starting at address with
- ensure CMOS is cleared.
lower bits to 0xFFF0
ISA
9a
cycles
to
Check RMRTCCS# & MEMRD#
Check directly on boot memory pin
boot memory
Verify MEMCS16#:
- must not be asserted for 8-bit memory
Verify IOCHRDY is not be asserted
Verify ISAOE# pin:
- it controls IDE / ISA bus demultiplexing
Check FCS0# & PRD#
8b
Local Bus
Check directly on boot memory pin
Verify HCLK speed and CPU clock mode.
cycles
9b
to
boot memory
Check, with a logic analyzer, that first
Local Bus cycles are the expected one:
memory read starting at the top of boot
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
memory less 16 bytes
- ensure CMOS is cleared.
The CPU fills its first cache line by fetching 16 bytes from boot memory.
Then, first instructions are executed from the CPU.
10
Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU
=> Minimum hardware is correctly set, CPU executes code.
Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.
Issue 1.0 - July 24, 2002
107/111
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