STPCI2(2002) 查看數據表（PDF） - STMicroelectronics

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STPCI2
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

STRAP OPTION

3.1. STRAP OPTION REGISTER DESCRIPTION

3.1.1. STRAP REGISTER 0

This register is read only.

STRAP0

7

MD[7]

Access = 0022h/0023h

Regoffset =04Ah

6

5

4

3

2

1

0

MD[6]

MD[9]

MD[8]

RSV

MD[5]

MD[4]

MD[17]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Bits 7-6

Bits 5-4

Bit 3

Bit 2

Bits 1-0

Mnemonic

MD[7:6]

MD[9:8]

Rsv

MD[5]

MD[4], MD[17]

Description

PCICLK PLL set-up: The value sampled on MD[7:6] controls the PCICLK

PLL programming according to the PCICLK frequency.

MD7 MD6

0 0 PCICLK frequency between 16 & 32 MHz

0 1 PCICLK frequency between 32 & 64 MHz

1 X Reserved

Mode selection:

MD9 MD8

0 0 ISA mode: ISA enabled, PCMCIA & Local Bus disabled

0 1 PCMCIA mode: PCMCIA enabled, ISA & Local Bus disabled

1 0 Local Bus mode: Local Bus enabled, ISA & PCMCIA disabled

1 1 Reserved

Reserved

Host Memory synchronization. This bit reflects the value sampled on

[MD5] and controls the MCLK/HCLK synchronization.

0: MCLK and HCLK not synchronized

1: MCLK and HCLK synchronized.

PCICLK division: These bits reflect the values sampled on [MD4] and

MD[17] to select the PCICLK frequency.

MD4 MD17

0 X PCI Clock output = HCLK / 4

1 0 PCI Clock output = HCLK / 3

1 1 PCI Clock output = HCLK / 2

Issue 1.0 - July 24, 2002

35/111

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