STPCI2GDYI(2002) 查看數據表（PDF） - STMicroelectronics

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STPCI2GDYI
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

3.1.5.

CPUCLK/HCKL

PROGRAMMING

DESKEW

;

MD[45]

1

0

MD[46]

Description

0

HCLK between 33MHz and

64MHz

1

HCLK between 64MHz and

133MHz

All other settings are reserved

Table 3-1.

Note that these straps are not accessible by

software.

STRAP OPTION

Issue 1.0 - July 24, 2002

39/111

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