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STPCI2HEYC(2002) 查看數據表(PDF) - STMicroelectronics

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STPCI2HEYC
(Rev.:2002)
ST-Microelectronics
STMicroelectronics 
STPCI2HEYC Datasheet PDF : 111 Pages
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ELECTRICAL SPECIFICATIONS
Table 4-14. ISA Bus AC Timing
Name Parameter
Min
10d Memory access to 8-bit ISA Slave
2T
10e
SA[19:0] & SBHE valid before IOR#, IOW# asserted
2T
11
ISACLK2X to IOW# valid
11a Memory access to 16-bit ISA Slave - 2BCLK
2T
11b Memory access to 16-bit ISA Slave - Standard 3BCLK
2T
11c Memory access to 16-bit ISA Slave - 4BCLK
2T
11d Memory access to 8-bit ISA Slave - 2BCLK
2T
11e
Memory access to 8-bit ISA Slave - Standard 3BCLK
2T
12
ALE# asserted before ALE# negated
1T
13
ALE# asserted before MEMR#, MEMW# asserted
13a Memory Access to 16-bit ISA Slave
2T
13b Memory Access to 8-bit ISA Slave
2T
13
ALE# asserted before SMEMR#, SMEMW# asserted
13c Memory Access to 16-bit ISA Slave
2T
13d Memory Access to 8-bit ISA Slave
2T
13e
ALE# asserted before IOR#, IOW# asserted
2T
14
ALE# asserted before AL[23:17]
14a Non compressed
15T
14b Compressed
15T
15
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
15a Memory Access to 16-bit ISA Slave- 4 BCLK
11T
15e Memory Access to 8-bit ISA Slave- Standard Cycle
11T
18a
ALE# negated before LA[23:17] invalid (non compressed)
14T
18a
ALE# negated before LA[23:17] invalid (compressed)
14T
22
MEMR#, MEMW# asserted before LA[23:17]
22a Memory access to 16-bit ISA Slave.
13T
22b Memory access to 8-bit ISA Slave.
13T
23
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
23b Memory access to 16-bit ISA Slave Standard cycle
9T
23e Memory access to 8-bit ISA Slave Standard cycle
9T
23
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
23h Memory access to 16-bit ISA Slave Standard cycle
9T
23l Memory access to 16-bit ISA Slave Standard cycle
9T
23
IOR#, IOW# asserted before IOR#, IOW# negated
23o Memory access to 16-bit ISA Slave Standard cycle
9T
23r Memory access to 8-bit ISA Slave Standard cycle
9T
24
MEMR#, MEMW# asserted before SA[19:0]
24b Memory access to 16-bit ISA Slave Standard cycle
10T
24d Memory access to 8-bit ISA Slave - 3BLCK
10T
24e Memory access to 8-bit ISA Slave Standard cycle
10T
24f Memory access to 8-bit ISA Slave - 7BCLK
10T
24
SMEMR#, SMEMW# asserted before SA[19:0]
24h Memory access to 16-bit ISA Slave Standard cycle
10T
24i Memory access to 16-bit ISA Slave - 4BCLK
10T
24k Memory access to 8-bit ISA Slave - 3BCLK
10T
24l Memory access to 8-bit ISA Slave Standard cycle
10T
Note: The signal numbering refers to Table 4-8
Max
Units
Cycle
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
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Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Issue 1.0 - July 24, 2002
55/111

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