STPCI2GDYI(2002) 查看數據表（PDF） - STMicroelectronics

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STPCI2GDYI
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

ELECTRICAL SPECIFICATIONS

Table 4-14. ISA Bus AC Timing

Name Parameter

Min

24

IOR#, IOW# asserted before SA[19:0]

24o I/O access to 16-bit ISA Slave Standard cycle

19T

24r I/O access to 16-bit ISA Slave Standard cycle

19T

25

MEMR#, MEMW# asserted before next ALE# asserted

25b Memory access to 16-bit ISA Slave Standard cycle

10T

25d Memory access to 8-bit ISA Slave Standard cycle

10T

25

SMEMR#, SMEMW# asserted before next ALE# asserted

25e Memory access to 16-bit ISA Slave - 2BCLK

10T

25f Memory access to 16-bit ISA Slave Standard cycle

10T

25h Memory access to 8-bit ISA Slave Standard cycle

10T

25

IOR#, IOW# asserted before next ALE# asserted

25i I/O access to 16-bit ISA Slave Standard cycle

10T

25k I/O access to 16-bit ISA Slave Standard cycle

10T

26

MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted

26b Memory access to 16-bit ISA Slave Standard cycle

12T

26d Memory access to 8-bit ISA Slave Standard cycle

12T

26

SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted

26f Memory access to 16-bit ISA Slave Standard cycle

12T

26h Memory access to 8-bit ISA Slave Standard cycle

12T

26

IOR#, IOW# asserted before next IOR#, IOW# asserted

26i I/O access to 16-bit ISA Slave Standard cycle

12T

26k I/O access to 8-bit ISA Slave Standard cycle

12T

28

Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted

28a Memory access to 16-bit ISA Slave

3T

28b Memory access to 8-bit ISA Slave

3T

28

Any command negated to IOR#, IOW# asserted

28c I/O access to ISA Slave

3T

29a

MEMR#, MEMW# negated before next ALE# asserted

1T

29b

SMEMR#, SMEMW# negated before next ALE# asserted

1T

29c

IOR#, IOW# negated before next ALE# asserted

1T

33

LA[23:17] valid to IOCHRDY negated

33a Memory access to 16-bit ISA Slave - 4 BCLK

8T

33b Memory access to 8-bit ISA Slave - 7 BCLK

14T

34

LA[23:17] valid to read data valid

34b Memory access to 16-bit ISA Slave Standard cycle

8T

34e Memory access to 8-bit ISA Slave Standard cycle

14T

37

ALE# asserted to IOCHRDY# negated

37a Memory access to 16-bit ISA Slave - 4 BCLK

6T

37b Memory access to 8-bit ISA Slave - 7 BCLK

12T

37c I/O access to 16-bit ISA Slave - 4 BCLK

6T

37d I/O access to 8-bit ISA Slave - 7 BCLK

12T

38

ALE# asserted to read data valid

38b Memory access to 16-bit ISA Slave Standard Cycle

4T

38e Memory access to 8-bit ISA Slave Standard Cycle

10T

38h I/O access to 16-bit ISA Slave Standard Cycle

4T

38l I/O access to 8-bit ISA Slave Standard Cycle

10T

Note: The signal numbering refers to Table 4-8

Max

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Issue 1.0 - July 24, 2002

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