STPCI2(2002) 查看數據表（PDF） - STMicroelectronics

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STPCI2
(Rev.:2002)

X86 Core PC Compatible System-on-Chip for Terminals

STMicroelectronics 

DESIGN GUIDELINES

6.4.4. PCI INTERFACE

6.4.4.2. PCI Clocking Scheme

6.4.4.1. Introduction

In order to achieve a PCI interface which work at

clock frequencies up to 33MHz, careful

consideration has to be given to the timing of the

interface with all the various electrical and

physical constraints taken into consideration.

The PCI Clocking Scheme deserves a special

mention here. Basically the PCI clock (PCICLKO)

is generated on-chip from HCLK through a

programmable delay line and a clock divider. The

nominal frequency is 33MHz. This clock must be

looped to PCICLKI and goes to the internal South

Bridge through a deskewer. On the contrary, the

internal North Bridge is clocked by HCLK, putting

some additionnal constraints on T0 and T1.

Figure 6-28. Clock Scheme

HCLK PLL

HCLK

clock

delay

1/2

1/3

1/4

MD[30:27] MD[17,4]

Strap Options

MD[7:6]

Deskewer

PCICLKO

PCICLKI

South

Bridge

North

Bridge

AD[31:0]

MUX

STPC

T0

T2

T1

98/111

Issue 1.0 - July 24, 2002

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