STPCI2 查看數據表（PDF） - STMicroelectronics
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STPCI2 Datasheet PDF : 108 Pages
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STPC® ATLAS
6.6. DEBUG METHODOLOGY
PCI_CLKI and PCI_CLKO must be connected as
described in Figure 6-29 and not be higher than
In order to bring a STPC-based board to life with
the best efficiency, it is recommended to follow the
check-list described in this section.
33MHz. Their speed depends on HCLK and on the
divider ratio defined by the MD[4] and MD[17] strap
options as described in Section 3.
To ensure a correct behaviour of the device, the
6.6.1. POWER SUPPLIES
PCI deskewing logic must be configured properly
by the MD[7:6] strap options according to Section
In parallel with the assembly process, it is useful to 3. For timings constraints, refers to Section 4.
get a bare PCB to check the potential short-circuits
between the various power and ground planes.
This test is also recommended when the first
1) MCLKI and MCLKO must be connected as
described in Figure 6-5 to Figure 6-7 depending on
boards are back from assembly. This will avoid the SDRAM implementation. The memory clock
bad surprises in case of a short-circuit due to a must run at HCLK speed when in synchronous
bad soldering.
mode and must not be higher than 90MHz in any
case. The MCLK interface will run 100MHz
When the system is powered, all power supplies, operation is possible but board layout is so critical
including the PLL power pins must be checked to that 90MHz maximum operation is recommended.
be sure the right level is present. See Table 4-2 for
the exact supported voltage range:
t(s) VDD_CORE: 2.5V
VDD_xxxPLL: 2.5V
c VDD: 3.3V
du 6.6.2. BOOT SEQUENCE
ro 6.6.2.1. Reset input
P The checking of the reset sequence is the next
te step. The waveform of SYSRSTI# must complies
le with the timings described in Figure 4-3. This
signal must not have glitches and must stay low
so until the 14.31818MHz output (OSC14M) is at the
b right frequency and the strap options are stabilized
to a valid configuration.
- O In case this clock is not present, check the 14MHz
) oscillator stage (see Figure 6-4).
t(s 6.6.2.2. Strap options
c The STPC has been designed in a way to allow
u configurations for test purpose that differs from the
rod functional configuration. In many cases, the
troubleshootings at this stage of the debug are the
P resulting of bad strap options. This is why it is
mandatory to check they are properly setup and
te sampled during the boot sequence.
ole The list of all the strap options is summarized at
s the beginning of Section 3.
b6.6.2.3. Clocks
OOnce OSC14M is checked and correct, the next
6.6.2.4. Reset output
If SYSRSTI# and all clocks are correct, then the
SYSRSTO# output signal should behave as
described in Figure 4-3.
6.6.3. ISA MODE
Prior to check the ISA bus control signals,
PCI_CLKI, ISA_CLK, ISA_CLK2X, and DEV_CLK
must be running properly. If it is not the case, it is
probably because one of the previous steps has
not been completed.
6.6.3.1. First code fetches
When booting on the ISA bus, the two key signals
to check at the very beginning are RMRTCCS#
and FRAME#.
The first one is a Chip Select for the boot flash and
is multiplexed with the IDE interface. It should
toggle together with ISAOE# and MEMRD# to
fetch the first 16 bytes of code. This corresponds
to the loading of the first line of the CPU cache.
In case RMRTCCS# does not toggle, it is then
necessary to check the PCI FRAME# signal.
Indeed the ISA controller is part of the South
Bridge and all ISA bus cycles are visible on the
PCI bus.
If there is no activity on the PCI bus, then one of
the previous steps has not been checked properly.
If there is activity then there must be something
signals to measure are the Host clock (HCLK), PCI conflicting on the ISA bus or on the PCI bus.
clocks (PCI_CLKO, PCI_CLKI) and Memory clock
(MCLKO, MCLKI).
6.6.3.2. Boot Flash size
The ISA bus supports 8-bit and 16-bit memory
HCLK must run at the speed defined by the
corresponding strap options (see Table 3-1). In x2
CPU clock mode, this clock must be limited to
66MHz.
devices. In case of a 16-bit boot flash, the signal
MEMCS16# must be activated during
RMRTCCS# cycle to inform the ISA controller of a
16-bit device.
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