STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

3.1.2 STRAP REGISTER 1

This register is read only.

STRAP1

7

MD[40]

Access = 0022h/0023h

Regoffset =04Bh

6

5

4

3

2

1

0

MD[14]

RSV

RSV

RSV

RSV

RSV

MD[36]

This register defaults to the values sampled on the MD pins after reset

Bit Number Sampled

Mnemonic

Description

CPU Clock Multiplication (486 mode):

MD14 MD40

1 0 X1

Bits 7-6

MD[40] & MD[14] 1 1 X 2

All other settings are reserved

t(s) Bits 5-1

Obsolete Product(s) - Obsolete Produc Bit 0

Rsv

MD[36]

HCLK maximum speed is 66MHz and in CPU mode X2.

Operation in X1 mode is only guaranteed up to 66MHz.

Reserved

These bits reflect the values sampled on MD[36] and determines the

Local Bus Boot device width:

0: 8-bit Boot Device

1: 16-bit Boot Device

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