STPCC01 查看數據表（PDF） - STMicroelectronics
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STPCC01 Datasheet PDF : 51 Pages
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4.5.1 AC Timing parameters
Table 4-4. PCI Bus AC Timing
Name
t1
t2
t3
t4
t5
T6
T7
T8
T9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
Parameter
PCI_CLKI to AD[31:0] valid
PCI_CLKI to FRAME# valid
PCI_CLKI to CBE#[3:0] valid
PCI_CLKI to PAR valid
PCI_CLKI to TRDY# valid
PCI_CLKI to IRDY# valid
PCI_CLKI to STOP# valid
PCI_CLKI to DEVSEL# valid
PCI_CLKI to PCI_GNT# valid
AD[31:0] bus setup to PCI_CLKI
AD[31:0] bus hold from PCI_CLKI
PCI_REQ#[2:0] setup to PCI_CLKI
PCI_REQ#[2:0] hold from PCI_CLKI
CBE#[3:0] setup to PCI_CLKI
CBE#[3:0] hold to PCI_CLKI
IRDY# setup to PCI_CLKI
IRDY# hold to PCI_CLKI
FRAME# setup to PCI_CLKI
FRAME# hold from PCI_CLKI
Table 4-5. DRAM Bus AC Timing
Name
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
Parameter
HCLK to RAS#[3:0] valid
HCLK to CAS#[7:0] bus valid
HCLK to MA[11:0] bus valid
HCLK to MWE# valid
HCLK to MD[63:0] bus valid
MD[63:0] Generic setup
GCLK2X to RAS#[3:0] valid
GCLK2X to CAS#[7:0] valid
GCLK2X to MA[11:0] bus valid
GCLK2X to MWE# valid
GCLK2X to MD[63:0] bus valid
MD[63:0] Generic hold
Table 4-6. IDE Bus AC Timing
Name
t20
t21
Parameter
DD[15:0] setup to PIOR#/SIOR# falling
DD[15:0} hold to PIOR#/SIOR# falling
ELECTRICAL SPECIFICATIONS
Min
Max
Unit
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
11
ns
2
12
ns
7
ns
0
ns
7
ns
4
ns
7
ns
0
ns
7
ns
0
ns
7
ns
0
ns
Min
Max
Unit
19
ns
19
ns
19
ns
17
ns
20
ns
13
ns
19
ns
19
ns
19
ns
17
ns
20
ns
0
ns
Min
Max
Unit
15
ns
0
ns
Issue 1.2
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