STPCC5HEBI 查看數據表（PDF） - STMicroelectronics
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STPCC5HEBI Datasheet PDF : 93 Pages
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3.1.4. CPC STRAP REGISTER 0 CONFIGURATION
STRAP OPTIONS
HCLK_Strap
7
MD[3}
Access = 0022h/0023h
Regoffset = 05Fh
6
5
4
3
2
1
0
MD[2]
MD[26]
MD[25]
MD[24]
Rsv
This register defaults to the values sampled on MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-3
These pins reflect the values sampled on MD[3:2] and
MD[3:2] & MD[26:24] MD[26:24] pins respectively and control the Host clock
frequency synthesizer as shown in Table 3-1
Bits 2-0
Rsv
Reserved
MD[3]
0
0
0
0
0
1
1
MD[2]
0
0
0
0
1
0
1
Table 3-1. HCLK Frequency Programming
MD[26]
0
0
0
0
0
0
0
MD[25]
0
0
1
1
0
1
0
MD[24]
0
1
0
1
1
1
1
HCLK Speed
25 MHz
50 MHz
60 MHz
66 MHz
75 MHz
90 MHz
100 MHz
Release 1.5 - January 29, 2002
31/93
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