STPCE1EDBI 查看數據表（PDF） - STMicroelectronics

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STPCE1EDBI

X86 Core General Purpose PC Compatible System - on - Chip

STMicroelectronics 

STRAP OPTION

3.1.3. STRAP REGISTER 2 CONFIGURATION

Strap2

7

Access = 0022h/0023h

Regoffset = 04Ch

6

5

4

3

2

1

0

Rsv

MD23

Rsv

MD19

MD18

MD17

MD16

This register defaults to the values sampled on MD[23] and MD[19:16] pins after reset

Bit Number Sampled

Bits 7-6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

Rsv

MD23

Rsv

MD19

MD18

MD17

MD16

Description

Reserved

Reserved

Reserved

Reserved

Reserved

This bit, programmed in parallel with MD[4], reflects the value sampled

on MD[17] pin and controls the PCI clock output, as given in Table 3-3.

Reserved

MD[4]

0

1

1

MD[17]

X

0

1

Table 3-3. PCI Clock Output

Description

PCI clock output = HCLK / 4

PCI clock output = HCLK / 3

PCI clock output = HCLK / 2

30/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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