STPCE1EDBI 查看數據表（PDF） - STMicroelectronics

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STPCE1EDBI

X86 Core General Purpose PC Compatible System - on - Chip

STMicroelectronics 

ELECTRICAL SPECIFICATIONS

4.5.2 RESET SEQUENCE

Figure 4-4 describes the reset sequence of the

STPC, also called warm reset.

The constraints on the strap options and the bus

activities are the same as for the cold reset.

The SYSRSTI# pulse duration must be long

enough to have all the strap options stabilized and

must be adjusted depending on resistor values.

Figure 4-4. Reset timing diagram

It is mandatory to have a clean reset pulse without

glitches as the STPC could then sample invalid

strap option setting and enter into an umpredicta-

ble mode.

While SYSRSTI# is active, the PCI clock PLL runs

in open loop mode at a speed of few 100’s KHz.

14 MHz

SYSRSTI#

ISACLK

Strap Options M D[63:0]

HCLK

PCI_CLK

SYSRSTO#

1.6 V

VALID CONFIGURATION

2.3 ms

Release 1.3 - January 29, 2002

39/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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