STPCE1EDBC 查看數據表（PDF） - STMicroelectronics
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STPCE1EDBC Datasheet PDF : 87 Pages
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4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS
Table 4-7 and Table 4-11 list the AC characteris-
tics of the ISA interface.
Figure 4-7 ISA Cycle (ref Table 4-11)
ELECTRICAL SPECIFICATIONS
ALE
AEN
LA [23:17]
SA [19:0]
CONTROL (Note 1)
IOCS16#
MCS16#
IOCHRDY
READ DATA
WRITE DATA
2
13
12
9
14
18
15
38
37
25
56
29
22
Valid AENx
3
Valid Address
34
33
42
11
24
41
10
Valid Address, SBHE*
57
27
23
48
47
61
26
55
58
59
28
64
VALID DATA
54
V.Data
Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
The clock has not been represented as it is dependent on the ISA Slave mode.
Table 4-11. ISA Bus AC Timing
Name Parameter
Min
2
LA[23:17] valid before ALE# negated
5T
3
LA[23:17] valid before MEMR#, MEMW# asserted
3a Memory access to 16-bit ISA Slave
5T
3b Memory access to 8-bit ISA Slave
5T
9
SA[19:0] & SBHE valid before ALE# negated
1T
10
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
10a Memory access to 16-bit ISA Slave
2T
10b Memory access to 8-bit ISA Slave
2T
10
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
10c Memory access to 16-bit ISA Slave
2T
Note: The signal numbering refers to Table 4-7
Max
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycle
Release 1.3 - January 29, 2002
43/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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