Table 4-5. DRAM Bus AC Timing
Name
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
Parameter
HCLK to RAS#[3:0] valid
HCLK to CAS#[7:0] bus valid
HCLK to MA[11:0] bus valid
HCLK to MWE# valid
HCLK to MD[63:0] bus valid
MD[63:0] Generic setup
GCLK2X to RAS#[3:0] valid
GCLK2X to CAS#[7:0] valid
GCLK2X to MA[11:0] bus valid
GCLK2X to MWE# valid
GCLK2X to MD[63:0] bus valid
MD[63:0] Generic hold
Table 4-6. PCI Interface AC TImings
Name
t13
t14
t15
t16
t17
Parameter
PCI_CLKI to FRAME# valid
PCI_CLKI to TRDY# valid
PCI_CLKI to IRDY# valid
PCI_CLKI to STOP# valid
PCI_CLKI to DEVSEL# valid
Table 4-7. Graphics Adapter (VGA) AC Timing
Name
t18
t19
Parameter
DCLK to VSYNC valid
DCLK to HSYNC valid
Table 4-8. IPC Interface AC Timings
Name
t20
t21
t22
t23
Parameter
XTALO to DACK_EN[2:0] valid
XTALO to TC valid
IRQ_MUX Input setup to ISACLK2X
DREQ_MUX[1:0] Input setup to ISACLK2X
ELECTRICAL SPECIFICATIONS
Min
Max
Unit
16
ns
16
ns
16
ns
16
ns
16
ns
9
ns
17
ns
17
ns
17
ns
17
ns
17
ns
5
ns
Min
Max
Unit
15
nS
15
nS
15
nS
15
nS
15
nS
Min
Max
Unit
27
ns
27
ns
Min
Max
Unit
71
nS
68
nS
0
-
nS
0
-
nS
Issue 1.1
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