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CL-PS7500FE 查看數據表(PDF) - Cirrus Logic

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CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
11.11.1 Programming the Timers
The locations of the registers can be found in Chapter 10.
A write to the following registers updates the values as described below:
T0low
updates the value in the lower half of the timer 0 input latch
T0high
updates the value in the upper half of the timer 0 input latch with the
written value.
T0GO
loads the counters immediately with the value programmed into the
input latch. If the counter is loaded with ‘0’ it is continuously reload.
T0LAT
places the current count value in the output latch.
A read of the following registers updates the values as described below:
T0high
returns the upper 8 bits of the count value
T0low
returns the lower 8 bits of the count value.
11.11.2 Timer interrupts
Each timer generates an interrupt when it reaches zero and is reloaded. These interrupts are handled by
the IRQA set of interrupt processing registers (bits 5 and 6).
The timers can be used to generate timed interrupts at regular intervals, T, where:
T = (T0low + (256 × T0high)) × 0.5 µs
Equation 11-1
11.12 General-Purpose, 8-Bit-Wide I/O Port
A general-purpose 8-bit-wide I/O port is included in the CL-PS7500FE. The eight open drain output pins
IOP[7:0] can be driven low or monitored as inputs by using the IOLINES register at address 0x0320000C.
When read, this register returns the current value seen at the IOP[7:0] pins. When written to, each bit con-
trols the status of the corresponding IOP pin. When a one is written to a bit, that pin's output enable is
switched off and it can be driven as an input. When a ‘0’ is written to a bit, the corresponding output pin
is forced low.
There is a complete set of three interrupt control and status registers (IRQD) for the IOP pins that allow
any bit to generate a unique interrupt. The interrupt is generated when the corresponding IOP bit is low.
120
I/O SUBSYSTEMS
ADVANCE DATA BOOK v2.0
June 1997

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