CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

20. BUS INTERFACE

20.1 Bus Arbitration

Arbitration for the main CL-PS7500FE data bus is carried out with the priorities shown below:

1) Video/cursor DMA

2) Sound DMA

3) DRAM refresh

4) ARM processor memory cycles

As the CL-PS7500FE contains a cached processor, ARM internal cycles can continue while DMA is in

progress, but the CPU stalls when it suffers a cache miss and requires to fill a cache line from memory.

Once an external memory cycle has started, DMA has to wait until it is completed. The exception is for

I/O reads or writes and SUSPEND mode, where the write data is latched internally at the start of the cycle,

then DMA requests can be serviced even though the I/O access or SUSPEND mode is under way. The

end of an I/O access is held up until the current DMA access is complete. I/O read data is latched inter-

nally when available, and is not enabled onto the CL-PS7500FE data bus until any DMA transfers have

completed.

20.2 Bus Cycle Types

There are a large number of different types of cycle that use of the CL-PS7500FE data bus. Except for

DMA accesses, the cycle type is decoded according to the address put out by the ARM processor mac-

rocell, and the detailed timing is controlled by the relevant section of the I/O or memory controller sub-

system.

The ARM processor supports two basic types of external cycle:

q Non-sequential consists of an idle cycle followed by a memory cycle

q Sequential

consists simply of a memory cycle

The idle cycle allows the memory and I/O controller subsystems time to prepare for a new cycle type.

These two cycles are used as the basic building block for the more complex I/O and memory access cycle

timings generated by the CL-PS7500FE. ARM processor external cycles are clocked by the internal

MEMCLK signal generated by the CL-PS7500FE memory controller according to the type of cycle.

Only the latched version of the ARM processor’s address is exported from the ARM processor, and this

can only change immediately after the falling edge of the internal MEMCLK signal that clocks the ARM

for external accesses. The timing diagrams in Chapter 22 include MEMCLK as a reference as it indicates

the end of a particular cycle. To save power, the CL-PS7500FE internal data bus is not always exported

during internal register programming.

The ARM processor requests an external memory access for a number of reasons:

q A cache line fetch always consists of memory reads from four sequential addresses.

q A Level 1 translation fetch consists of a read from memory followed by the address translation so that the

next address output by the ARM is the translated physical address as generated from the read-back section

descriptor.

q A Level 2 translation fetch is always preceded by a Level 1 fetch, and returns the page table entry, then used

to create the physical address for the next cycle.

June 1997

ADVANCE DATA BOOK v2.0

BUS INTERFACE

187

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