Z86E4016KSC 查看數據表（PDF） - Zilog

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Z86E4016KSC

Z8 4K OTP MICROCONTROLLER

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Z86E30/E31/E40

Z8 4K OTP Microcontroller

(Figures 33 and 34). After this point, the register cannot be WDTMR cannot be read and is located in Bank F of the Ex-

modified by any means, intentional or otherwise. The panded Register Group at address location 0FH.

1

WDTMR (F) 0F

D7 D6 D5 D4 D3 D2 D1 D0

* Default setting after RESET

WDT TAP

00

01 *

10

11

INT RC OSC

5 ms

10 ms

20 ms

80 ms

System Clock

128 SCLK

256 SCLK

512 SCLK

2048 SCLK

WDT During HALT

0 OFF

1 ON *

WDT During STOP

0 OFF

1 ON *

XTAL1/INT RC Select for WDT

0 On-Board RC *

1 XTAL

Reserved (Must be 0)

Figure 33. Watch-Dog Timer Mode Register

Write Only

DS97Z8X0500

PRELIMINARY

47

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