Z8018220ASC 查看數據表（PDF） - Zilog
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Z8018220ASC Datasheet PDF : 109 Pages
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Zilog
DMA REGISTERS (Continued)
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Bit
Upon Reset
R/W
DSTAT
DE1 DE0 /DWE1 /DWE0 DIE1
0
0
1
1
0
R/W R/W W W R/W
DIE0
0
R/W
Addr 30H
- DIME
10
R
DMA Master Enable
DMA Interrupt Enable 1, 0
DMA Enable Bit Write Enable 1, 0
DMA Enable Ch 1, 0
Figure 40. DMA Status Register
Bit
Upon Reset
R/W
DMODE
-
-
1
1
Addr 31H
DM1 DM0 SM1 SM0 MMOD -
0
0
0
0
0
1
R/W R/W R/W R/W R/W
Memory MODE Select
Ch 0 Source Mode 1, 0
Ch 0 Destination Mode 1, 0
DM1, 0
00
01
10
11
Destination
M
M
M
I/O
Address
DAR0+1
DAR0-1
DAR0 Fixed
DAR0 Fixed
MMOD
0
1
Mode
Cycle Steal Mode
Burst Mode
SM1, 0
00
01
10
11
Source
M
M
M
I/O
Address
SAR0+1
SAR0-1
SAR0 Fixed
SAR0 Fixed
Figure 41. DMA Mode Registers
3-40
PS009801-0301
DS971820600
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