STM32F103V8H6TR 查看數據表（PDF） - STMicroelectronics

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STM32F103V8H6TR

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

STMicroelectronics 

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

FSMC_NEx

tw(NE)

FSMC_NOE

FSMC_NWE

FSMC_A[25:0]

FSMC_NBL[1:0]

FSMC_D[15:0]

FSMC_NADV(1)

tv(NWE_NE)

tw(NWE)

tv(A_NE)

tv(BL_NE)

tv(Data_NE)

t v(NADV_NE)

tw(NADV)

th(A_NWE)

Address

th(BL_NWE)

NBL

th(Data_NWE)

Data

t h(NE_NWE)

ai14990

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)

Symbol

Parameter

Min

Max

Unit

tw(NE)

FSMC_NE low time

3THCLK – 1 3THCLK + 2 ns

tv(NWE_NE) FSMC_NEx low to FSMC_NWE low

THCLK – 0.5 THCLK + 1.5 ns

tw(NWE)

FSMC_NWE low time

THCLK – 0.5 THCLK + 1.5 ns

th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK

ns

tv(A_NE)

FSMC_NEx low to FSMC_A valid

7.5

ns

th(A_NWE) Address hold time after FSMC_NWE high

THCLK

ns

tv(BL_NE)

FSMC_NEx low to FSMC_BL valid

1.5

ns

th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK – 0.5

ns

tv(Data_NE) FSMC_NEx low to Data valid

THCLK + 7

ns

th(Data_NWE) Data hold time after FSMC_NWE high

THCLK

ns

tv(NADV_NE) FSMC_NEx low to FSMC_NADV low

5.5

ns

tw(NADV)

FSMC_NADV low time

THCLK + 1.5 ns

1. CL = 15 pF.

2. Based on characterization, not tested in production.

Doc ID 14611 Rev 7

63/123

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